سال انتشار: ۱۳۸۳
محل انتشار: دهمین کنفرانس سالانه انجمن کامپیوتر ایران
تعداد صفحات: ۴
omid kavehie – department of electrical computer engineering shahid beheshti university
keivan navi –
implementation of parallel multipliers with operands meeting IEEE754 standard could involve a 27-2 compression of partial products . In this paper we offer a new design which is suitable for low power and high speed processing environment more than 41% of carry-in/carry-out wires are eliminated in our design with the advantage of less carry propagation delay and quite fewer interconnctions leading to faster multi;ocation and less chip area. our multiplier is coded in VHDL and implemented on commercially available EDA tool chain.