سال انتشار: ۱۳۸۳

محل انتشار: دوازدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۵

نویسنده(ها):

J. Jafari – IC Design Lab., ECE Dept., University of Tehran
A Amirabadi – IC Design Lab., ECE Dept., University of Tehran
A. Afzali-Kusha – IC Design Lab., ECE Dept.,University of Tehran

چکیده:

In this paper, a new technique for reducingthe subthreshold leakage current of CMOS VLSI circuits is proposed. It makes use of the fact that leakage currents of gates are depended on their input patterns. The order of gate input lines is manipulated to reduce the leakage current. The key feature of the method is that it does not have any overhead on the area or the speed. Also, it does not affect the dynamic
power consumption of the gate. The execution time for the algorithm determining the primary input order is also very fast. Up to 12% of the static power reduction is achieved by applying this method to ISCAS85 benchmark circuits.