سال انتشار: ۱۳۸۴

محل انتشار: سیزدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۴

نویسنده(ها):

Samiei – Department of Computer Eng. and Information Technology, Amirkabir University of Technology
Pedram – Department of Computer Eng. and Information Technology, Amirkabir University of Technology
Naderi – Department of Computer Eng. and Information Technology, Amirkabir University of Technology
Salehi – Department of Computer Eng. and Information Technology, Amirkabir University of Technology

چکیده:

This paper presents a fully asynchronous 1k´۴bit memory array with no assumption regarding to gate delays; thus suitable for systems with considerable changes in the voltage level and the environmental variables. The nominal voltage level was 3.3v, and it is shown that the design can still operate properly at the voltage levels as low as 1.2v. The design is based on QDI timing model and implemented using the Martin method.