سال انتشار: ۱۳۸۳

محل انتشار: دوازدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۶

نویسنده(ها):

A Zahabi – ECE Department University of Tehran
Y Koolivand – ECE Department University of Tehran
A Afzali-kusha – ECE Department University of Tehran
M Nourani – EE Department University of Texas

چکیده:

A new design methodology for dual Vt domino logic design based on noise, area and power constraints is presented. We have proposed the optimum ranges for the evaluation network tree are Wmin<WN1<4Wmin and 3Wmin<WN2<5Wmin which lead to dynamic power and area improvements about 13% and 33%, respectively. All results are based on HSPICE simulation with 0.25μm CMOS technology and
operating frequency of 1GHz.