سال انتشار: ۱۳۸۴
محل انتشار: سیزدهیمن کنفرانس مهندسی برق ایران
تعداد صفحات: ۴
Vahidfar – IC Design Laboratory, Department of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran
Fakhraie – IC Design Laboratory, Department of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran
12- bit phase value direct digital synthesizer (DDS). The DDS is enhanced by a one-bit second order digital delta sigma modulator to achieve high SFDR by reduction of the spur coming from phase truncation. This modulator removes the periodic phase truncation errors by noise shaping and dithering. For Area efficiency, the area of look up table ROM is highly reduced by using compression algorithms and quarter phase symmetry of sinusoidal signals.
The simulation results show more than 100 dB SFDR for 10-bit Sinusoid output at fclk/4 with 24 bit ACC and 12-bit phase truncation. This result shows about 29dB SFDR improvement in comparison to non shaped conventional DDS based modulators.