سال انتشار: ۱۳۸۵
محل انتشار: دوازدهمین کنفرانس سالانه انجمن کامپیوتر ایران
تعداد صفحات: ۶
Nasim Zeinolabedini – Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Shaahin Hessabi – Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
In this paper, we present a cycle-accurate co-simulation environment developed for verification and performance evaluation of OO-ASIP in our ODYSSEY design methodology. This environment is composed of a processor Instruction Set Simulator (ISS) integrated with a hardware simulator and communicate with it through socket connections. We demonstrate the effect of our co-simulation method in increasing speed of
simulation without missing cycle accuracy of results by means of two case studies.