سال انتشار: ۱۳۸۵
محل انتشار: چهاردهمین کنفرانس مهندسی برق ایران
تعداد صفحات: ۶
Ali Mahjur – Computer Engineering Department Sharif University of Technology Tehran, Iran
Yousef Ebrahimi – Computer Engineering Department Sharif University of Technology Tehran, Iran
Amir Hossein Jahangir –
Cache access is in the critical path of a superscalar execution. Therefore, not only its hit rate but also its access time is vital for the performance of a superscalar processor. Although direct-mapping, due to lower access time, is very suitable for L1 data caches, their lower hit rate prevents using them for this purpose. The proposed methods for boosting the hit rate of direct-mapped caches often increase the access time, or add an extra cycle. Therefore, they are seldom better than a set associative cache. This paper introduces a novel approach to increase the performance of direct-mapped caches. It predicts when a data block may be safely evicted. Then, it predicts the block that should be fetched to replace the evicted block. The approach does not change the access time. Measurements performed using SPEC CPU 2000 benchmarks show that the performance of this method is very close, and even in many cases, the same as a 2-way set associative cache with the same size. However, its simplicity of use as a direct mapping technique can be considered as its major advantage.