سال انتشار: ۱۳۸۰
محل انتشار: چهارمین کنفرانس دانشجویی مهندسی برق ایران
تعداد صفحات: ۱۱
hassan ghasemzadeh – university of tehran
in this paper we consider some of the issues that are involved in the implementation of highly optimized cache memorise and survey the techniques that can be used to help achieve lower miss rate in modern processors also we have an evaluation of cahe parameters that lead us to have an optimized cache memory . finally we present a cahe memory architecture obtained from the evaluation results and cahe improvement algorithms. this architecture takes the advantage of a victim cache and LRU block replace ment policy to improve miss rate.