سال انتشار: ۱۳۸۶

محل انتشار: پانزدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۶

نویسنده(ها):

Sarang Kezemi Nia – Microelectronics Research Center, Urmia University , Urmia , Iran
Ghaznavi-Ghoushchi – Microelectronics Research Center, Urmia University , Urmia , Iran

چکیده:

In hardware description languages (HDL), modular design and reuse of the previously designed components are widely used. It impacts on the time – To- Market and life – cycle of the design components. In this paper we present amethod to extract software intellectual properties (IP) from a given HDL design. The extracted IP cores are in perlilog [1]templates which can be used for a new binding by perlilon . our proposed approach gives a systematic procedure in extraction, top-down bunding and reuse of HDL modules. A new framework for declaration of modules is introduced. Experimentalresults of applying the proposed algorithms on a set of complete HDL designs are also presented.