سال انتشار: ۱۳۸۴

محل انتشار: سیزدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۵

نویسنده(ها):

Mehrdad Najibi – Department of Computer Engineering, Amirkabir University of Technology 424, Hafez Ave, Tehran 15914, Iran
Mohsen Naderi – Department of Computer Engineering, Amirkabir University of Technology 424, Hafez Ave, Tehran 15914, Iran
Hossein Pedram – Department of Computer Engineering, Amirkabir University of Technology 424, Hafez Ave, Tehran 15914, Iran
Mehdi Sedighi – Department of Computer Engineering, Amirkabir University of Technology 424, Hafez Ave, Tehran 15914, Iran

چکیده:

In this paper we present an automatic design tool for synthesizing Verilog behavioral description of an asynchronous circuit into delay insensitive presynthesized library modules, using syntax directed techniques. Our design tool can also generate appropriate output to support implementing the circuit on ASICs and LUT-based FPGAs and rapid prototyping of the asynchronous circuit is readily available.