سال انتشار: ۱۳۸۴

محل انتشار: سیزدهیمن کنفرانس مهندسی برق ایران

تعداد صفحات: ۷

نویسنده(ها):

Mehrdad Najibi – Computer Engineering Department, Amirkabir University of Technology (Tehran Polytechnic) 424 Hafez Ave, Tehran 15785, Iran
Kamran Saleh – Computer Engineering Department, Amirkabir University of Technology (Tehran Polytechnic) 424 Hafez Ave, Tehran 15785, Iran
Mohsen Naderi – Computer Engineering Department, Amirkabir University of Technology (Tehran Polytechnic) 424 Hafez Ave, Tehran 15785, Iran
Hossein Pedram – Computer Engineering Department, Amirkabir University of Technology (Tehran Polytechnic) 424 Hafez Ave, Tehran 15785, Iran

چکیده:

This paper introduces a methodology for prototyping Globally Asynchronous Locally Synchronous (GALS) circuits on synchronous commercial FPGAs. A library of required elements for implementing GALS circuits is proposed and general design considerations to successfully implementa GALS circuit onFPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different mplementationsof these circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder
as a practical example. The results show that the GALS approach improves the performance of the circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the circuit is increased by 51% which is acceptable considering that a pure synchronous circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.